User profiles for Abhay Saxena

Abhay Saxena

Dev Sanskriti Vishwavidyalaya
Verified email at dsvv.ac.in
Cited by 518

[PDF][PDF] Emergence of educators for Industry 5.0: An Indological perspective

A Saxena, D Pant, A Saxena, C Patel - Int. J. Innov. Technol. Explor …, 2020 - academia.edu
In the amid Covid-19 crisis where the world is suffering from the pandemic, the technology
is ready to march forward with the new vision, concepts, and principles. The Covid-19 crisis …

[PDF][PDF] Emergence of Futuristic HRM in Perspective of Human-Cobot's Collaborative Functionality

A Saxena, A Saxena, R Sharma… - International Journal of …, 2021 - researchgate.net
Industry 4.0 buzzed out with a theme of “Smart Manufacturing for the Future”. With the advent
of Industry 5.0, the world of technology is registering a paradigm shift from Customization to …

[PDF][PDF] Predicting intraday trading volume and volume percentages

V Satish, A Saxena, M Palmer - The journal of trading, 2014 - smallake.kr
This article discusses recent tech-niques and results in the area of forecasting intraday volume
and intraday volume percentages. Why predict volume? A major reason is to improve the …

[PDF][PDF] Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA

A Saxena, S Gaidhani, A Pant… - International Journal of …, 2015 - researchgate.net
Reducing the power consumption is the main concern in green computing. So here we used
capacitance scaling technique on comparator for optimizing the power. We worked with I/O …

Leakage power reduction with various IO standards and dynamic voltage scaling in vedic multiplier on Virtex-6 FPGA

B Pandey, MA Rahman, A Saxena… - Indian Journal of Science …, 2016 - ischolar.sscldl.in
The 8-bit design is able to process 256 times input combination in compare to 4-bit vedic
multiplier, using approximates 6 times basic elements, 2 times IO buffers, approximate 1.5 times …

High performance FIFO design for processor through voltage scaling technique

A Saxena, A Bhatt, P Gautam, P Verma… - Indian Journal of …, 2016 - ischolar.sscldl.in
Green computing is making revolution by bringing high speed processor with less power
consumption. Our paper is based on this philosophy. Objectives: To come out High …

HSTL IO Standards Based Processor Specific Green Counter Design on 90nm FPGAAbhay Saxena

A Saxena, AK Bhatt, B Pandey, P Tripathi… - International Journal of …, 2016 - earticle.net
Extending battery life and increase in portability of modern electronic devices and gadgets
are the main motives behind the Green Computing which is also known by similar terms like …

[PDF][PDF] SSTL Based Energy Efficient FIFO Design for High Performance Processor of Portable Devices

A Saxena, SK Sharma, P Agarwal… - International Journal of …, 2017 - researchgate.net
Now days green computing is major research area in the computer science field, where we
want to reduce the total power consumption of our device by applying different techniques. …

Energy Efficient CRC Design for Processor of Workstation, and Server using LVCMOS

A Saxena, C Patel, MSA Khan - Indian Journal of Science and …, 2017 - ischolar.sscldl.in
In our work we have designed CRC using the LVCMOS IO standards which are stands for
Low Voltage Complementary Metal Oxide Semiconductor. In this work we have worked with …

Dielectric relaxation studies in 5CB nematic liquid crystal at 9 GHz under the influence of external magnetic field using microwave cavity spectrometer

M Johri, A Saxena, S Johri, S Saxena, DP Singh - Pramana, 2011 - Springer
Resonance width, shift in resonance frequency, relaxation time and activation energy of 5CB
nematic liquid crystal are measured using microwave cavity technique under the influence …