Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
… a simple register re-indexing that augments the original register … register ID and the
corresponding warp ID to form a register … The total 10-bit register address (for 1,024 warp …
corresponding warp ID to form a register … The total 10-bit register address (for 1,024 warp …
Two-dimensional array of microtraps with atomic shift register on a chip
… Until now, however, atom chip experiments have focused on … using a simple magnetic-film
atom chip. We are able to load … chip surface utilizing the atom chip as an atomic shift register …
atom chip. We are able to load … chip surface utilizing the atom chip as an atomic shift register …
Performance evaluation of on-chip register and cache organizations
RJ Eickenmeyer, JH Patel - ACM SIGARCH Computer Architecture News, 1988 - dl.acm.org
… chip area tradeoffs between several register … chip [HiSm84, GoHs86]. Other researchers
have proposed architectures to cache stack data [DiMc82, Alpe84, StWeS’l]. Multiple Register …
have proposed architectures to cache stack data [DiMc82, Alpe84, StWeS’l]. Multiple Register …
Register organization for enhanced on-chip parallelism
R Sangireddy - Proceedings. 15th IEEE International …, 2004 - ieeexplore.ieee.org
… register value only for the purpose of analyzing the register activity during lifetime of its allocation
to a logical register… time of last consumption of a register. To study a relationship among …
to a logical register… time of last consumption of a register. To study a relationship among …
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication
Y Nakamura, K Hosokawa, I Kuroda… - Proceedings of the 41st …, 2004 - dl.acm.org
… of shared registers, … register architecture for communication between the C/C++ simulator
and emulator. We discuss examples of application of our co-verification system to actual chip-…
and emulator. We discuss examples of application of our co-verification system to actual chip-…
An area model for on-chip memories and its application
JM Mulder, NT Quach, MJ Flynn - IEEE Journal of Solid-State …, 1991 - ieeexplore.ieee.org
… 3(a) shows the area model of a register buffer or on-chip memory. The total area in … all
register buffers (or register files) unless otherwise stated. Large on-chip buffers, other than register …
register buffers (or register files) unless otherwise stated. Large on-chip buffers, other than register …
An architecture of a dataflow single chip processor
… It has a register file whose member is the strongly connected register … is limited by current
chip fabrication technology. Our chip contains 50,000 CMOS gates and 256 signal lines. …
chip fabrication technology. Our chip contains 50,000 CMOS gates and 256 signal lines. …
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register
Y Idei, K Shimohigashi, M Aoki, H Noda… - IEEE Journal of Solid …, 1998 - ieeexplore.ieee.org
… in a PROM mode register implemented in the chip periphery. … signal from the PROM register.
The effective refresh period can … Data-retention current of a 64-Mb DRAM test chip featuring …
The effective refresh period can … Data-retention current of a 64-Mb DRAM test chip featuring …
The effect of register-transfer design tradeoffs on chip area and performance
JJ Granacki, AC Parker - 20th Design Automation Conference …, 1983 - ieeexplore.ieee.org
… area consumption and performance at the register-transfer … Six register transfer level
designs were used in the experiment. Z … Thus, we chose these six as examples of register-transfer …
designs were used in the experiment. Z … Thus, we chose these six as examples of register-transfer …
[PDF][PDF] A Register Communication Mechanism for Speculative Multithreading Chip Multiprocessors
ND Barli, D Tashiro, C Iwama, S Sakai… - Proc. of the SACSIS …, 2003 - lab.iisec.ac.jp
… a register communication mechanism required to handle inter-thread register dependencies
… opcodes, each can pack int register 0 to 15, int register 16 to 31, fp register 0 to 15, and fp …
… opcodes, each can pack int register 0 to 15, int register 16 to 31, fp register 0 to 15, and fp …